1. Field of the Invention
The present invention relates to a Static Random Access Memory (SRAM), particularly to a Shadow RAM having a memory cell constituted by adding a ferroelectric capacitor to SRAM for reading and writing an SRAM cell at high speed when power is supplied and keeping nonvolatile storage in the ferroelectric capacitor when power is not supplied.
2. Description of the Prior Art
A conventional Static Random Access Memory (SRAM) includes a flip flop by two of inverters of CMOS as shown by, for example, a circuit diagram of FIG. 1A. Further, drains of NMOS transistors Q0 and Q1 constituting the flip flop, are made to constitute storage nodes N0 and N1. The two storage nodes N0 and N1 are connected to a negative bit line BLN and a positive bit line BLT via NMOS transistors Q4 and Q5 respectively functioning as transfer gates. Respective gates of the NMOS transistors Q4 and Q5 constituting the transfer gates, are connected to a common word line WL. The negative bit line BLN and the positive bit line BLT are paired and a sense amplifier, not illustrated, for comparing and amplifying voltages of the two bit lines, is connected therebetween.
Meanwhile, a Shadow RAM is constituted by adding ferroelectric capacitors to the storage nodes N0 and N1 of the above-described SRAM (hereinafter, simply referred to as SRAM). FIG. 1B is a circuit diagram of an example of a Shadow RAM described in Japanese Patent Laid-Open No. 2000-293989. Portions the same as those of SRAM shown in FIG. 1A are designated by the same notations and an explanation thereof will be omitted. According to the Shadow RAM, respective ends on one side of the ferroelectric capacitors F0 and F1 are connected to the two storage nodes N0 and N1 and both of ends on other side of the respective ferroelectric capacitors F0 and F1 are connected to a plate line PL. The plate line PL is connected to a plate line drive circuit outside of the drawing.
When power is supplied, the Shadow RAM is set to xc2xd of power source voltage Vcc, that is, Vcc/2 and reading and writing data executed in supplying power, are carried out similar to a conventional general SRAM. When power source is cut, there is carried out store operation of switching to shift data stored by the flip flop to polarizing directions of the ferroelectric capacitors F0 and F1. In a store period of time, stored data is stored as directions of remanent polarization of the ferroelectric capacitors F0 and F1 by driving the plate line PL to Vcc/2 to Vcc, further to 0V while maintaining the word line W in an inactivated state. Further, when power source is started, there is carried out recall operation of switching to shift data held by the ferroelectric capacitors to the flip flop. In a recall period of time, data stored by the ferroelectric capacitors as remanent polarization is reproduced to the flip flop by starting the power source of the flip flow while maintaining the word line WL and the plate line P1 in an inactivated state. In this way the Shadow RAM can function as a nonvolatile memory by which data stored by the flip flop is preserved even after having been subjected to cutting and restarting power source and in the meantime, reading and writing data can be carried out similar to the conventional SRAM.
In order to form such a Shadow RAM on a semiconductor substrate (silicon substrate), it is necessary to form the ferroelectric capacitor at a layer as upper as possible. Because in a ferroelectric capacitor, a ceramic thin layer is generally used as a dielectric insulating film between a lower electrode and an upper electrode and since the ferroelectric film is made of an oxide, when the ferroelectric film is exposed to a deoxidizing atmosphere, oxygen deficiency is brought about, resistance is reduced, leak current between electrodes is increased and a reduction in a ferroelectric polarizing amount, a reduction in a dielectric constant and a deterioration in other electric properties are brought about. Therefore, the ferroelectric capacitor is arranged at an uppermost layer of a multilayer wiring structure to be able to be formed after various metals of wiring layers have been formed such that the ferroelectric capacitor is not exposed to the deoxidizing atmosphere.
A sectional view of FIG. 10 shows a section taken along a line AAxe2x80x2 of FIG. 11A and respective views of FIGS. 11A, 11B and 11C and FIGS. 12A and 12B are views viewed along lines a through e of the sectional view. In FIG. 10, there is constructed a constitution in which a transistor level 300 formed with an MOS transistor is provided on a silicon substrate 1 and above the transistor level 300, there are provided multilayers of wiring layers successively laminated and formed with a first interlayer insulating film 311, a first wiring level 301, a second interlayer insulating film 312, a second wiring level 302, a third interlayer insulating film 313, a third wiring level 303, a fourth interlayer insulating film 314, a ferromagnetic capacitor level (a fourth wiring level) 304, a fifth interlayer insulating film 315, a fifth wiring level 305, and a passivation film 316.
FIG. 11A shows the transistor layer 300 comprising an N-type diffusion layer 321 and a P-type diffusion layer 322 and polysilicon wirings of a gate electrode 323 and a word line (WL) 324 formed at the silicon substrate 1. FIG. 11B shows the first wiring level 301 comprising a first relay wiring 326 connected to the respective diffusion layers 321 and 322 of the transistor layer 300 via a first plug 325. Further, the plug connects the upper layer 326 and the lower layers 321 and 322 to each other by filling a conductive material to a contact formed at the interlayer insulating film. FIG. 11C shows the second wiring level 302 comprising a power source line (Vcc) 328 connected to the first wiring level 301 by a second plug 327, a GND line 329, a second word line (WL) 330 connected in parallel with the word line 324 of the transistor layer 300 to reduce resistance of a total of the word line, and a second relay wiring 331 connected to the first relay wiring 326.
FIG. 12A shows the third wiring level 303 comprising bit lines (BLN, BLT) 333 connected to the second wiring level 302 by a third plug 332, a third relay wiring 334 connected to the second relay wiring 331. FIG. 12B shows the fourth wiring level 304 comprising a ferroelectric capacitor 336 connected to the third relay wiring 334 by a fourth plug 335, and the fifth wiring level 305 comprising a plate line (PL) 341 of an upper layer by a fifth plug 340 further thereabove. The ferroelectric capacitor 336 is constituted by a laminated layer structure of a lower electrode 337, a ferroelectric insulating film 338 and an upper electrode 339, the lower electrode 337 is connected to the third relay wiring 334 and the upper electrode 334 is connected to the plate line 341.
In this way, according to the above-described Shadow RAM (hereinafter, referred to as conventional type Shadow RAM), in order that the ferroelectric capacitors 336 are connected to the respective storage nodes N0 and N1 of the NMOS transistors Q0 and Q1 constituting the inverters, there is formed a structure in which the transistor layer 300 is connected to the lower electrode 337 of the ferroelectric capacitor 336 via the first through the fourth interlayer insulating films 311 through 334. That is, respectives of the first through the third wiring level 301 through 303 are formed with the first through the third relay wirings 326, 331 and 334 and the first through the fourth interlayer insulating films 311 through 314 are formed with the plugs 325, 327, 332 and 335.
In this way, according to the Shadow RAM, the first through third wiring levels 301 through 303, there is needed a space for arranging the respective relay wirings 326, 331 and 334 in addition to wirings needed for constituting SRAM and a cell area requested for a single memory cell MC is enlarged. As a result, there is constituted a hazard in achieving high capacitance formation of the storage capacitor of the Shadow RAM.
An explanation will be given of a structure of SRAM shown in FIG. 1A in reference to FIG. 13 through FIG. 15B for comparison. FIG. 13 is a vertical sectional view thereof, FIGS. 14A and 14B and FIGS. 15A and 15B are layout views viewed along lines a through d there of and there is constituted SRAM of a four-layers structure. In FIG. 13, there is constructed a constitution in which there is provided a transistor layer 400 formed with an MOS transistor on a silicon substrate 1, above the transistor layer 400, there is provided multilayers of wiring layers successively laminated with a first interlayer insulating film 411, a first wiring layer 401, a second interlayer insulating film 412, a second wiring layer 402, a third interlayer insulating film 413, a third wiring layer 403, and a passivation film 414.
FIG. 14A shows the transistor layer 400 having an N-type diffusion layer 421 and a P-type diffusion layer 422 formed at the silicon substrate 1 and polysilicon wiring of a gate electrode 423 and a word line 424. FIG. 14B shows the first wiring layer 401 comprising a first relay wiring 426 connected to the respective diffusion layers 421 and 422 of the transistor layer 400 via a first plug 425. FIG. 15A shows the second wiring layer 402 comprising a power source line (Vcc) 428 and a GND line 429 connected to the first relay wiring 426 via a second plug 427, a second word line (2 WL) 430 connected in parallel with the work line 424 of the transistor layer 400 for reducing resistance of a total of the work line and a second relay wiring 431. FIG. 15B is a third wiring layer 403 comprising bit lines (BLN, BLT) 433 connected to the second relay wiring 431 via a third plug 432.
When respective layers of SRAM of the four-layer structure and conventional type Shadow RAM are compared, it is known that in the case of the conventional type Shadow RAM, other than the power source line 328, the GND line 329 and the second word line 330, there is needed the second relay wiring 331 as an extra of a number of the wirings in the second wiring layer 402 of SRAM shown in FIG. 13 and other than the bit lines 333 in the third wiring level 303, there is needed the third relay wiring 334 as an extra of a number of the wirings in the third wiring level 303 of SRAM. It is possible in design to constitute a Shadow RAM by arranging wirings in correspondence with the second relay wiring and the third relay wiring needed as extras in the Shadow RAM respectively at the second wiring layer and the third wiring layer without changing the layout in SRAM of the four-layers structure. However, an interval between contiguous wirings is narrowed, and there is not provided a margin in forming a wiring layer in the photolithography technology to thereby cause shortcircuit between contiguous wirings. Particularly, in the third wiring layer, whereas in the case of SRAM, two pieces of the bit lines are aligned, in the case of the conventional type Shadow RAM, there are arranged the third relay wirings 334 to be electrically connected to the ferroelectric capacitors at the upper layer in a state of being provided along respectives of two pieces of the paired bit lines 333 and therefore, it is requested to increase the interval between the bit lines by that amount. Therefore, in accordance with increasing the interval between the bit lines, there is changed the layout of all the wiring layers including the transistor layer at the lowermost layer and in view of a length LW in a direction of extending the word line and a length LB in a direction of extending the bit line, the length LW in the direction of extending the word line of the Shadow RAM, becomes longer than a length of a memory cell of SRAM and a cell area of the memory cell above the semiconductor substrate is increased in comparison with that of SRAM. Further, by increasing the cell area of the memory cell, it is necessary to change a peripheral circuit of the memory cell such as a decoder, a sense amplifier and the like a scale of changing in design is enlarged and a number of design steps is increased.
Further, as illustrated in FIGS. 16A, 16B and 16C, there is proposed SRAM of a three-layers wiring structure reducing a number of layers. In the case of SRAM of the three-layers wiring structure, while a cell area of a memory cell thereof is made more or less larger than the cell area of SRAM shown in FIG. 13 through FIG. 15C, a number of wiring levels is reduced. The same notations are attached to portions of layout views of respective layers illustrated in FIGS. 16A, 16B and 16C equivalent to those of SRAM illustrated in FIG. 13 through FIG. 15C. FIG. 16A shows a transistor layer 400 having the respective N-type and P-type diffusion layers 421 and 422 formed at the silicon substrate 1 and the polysilicon wirings of the gate electrode 423 and the word line 424. FIG. 16B shows a first wiring layer 401 comprising the power source line 428, the second word line 430, and the first relay wiring 426 connected to the respective diffusion layers 421 of the transistor layer 400 via the first plug 425. FIG. 16C shows a third wiring layer 403 comprising the GND line 429 and the bit lines 433 connected via the first relay wiring 426.
FIGS. 17A and 17B and FIGS. 18A and 18B show layout views of a Shadow RAM in contrast to SRAM of the three-layers structure. Further, the same notations are attached to portions equivalent to those of FIG. 10 through FIG. 12B. FIG. 17A shows a transistor layer 300 having the respective N-type and P-type diffusion layers 321 and 322 formed at the silicon substrate 1 and the polysilicon wirings of the gate electrode 323 and the word line 324. FIG. 17B shows a first wiring level 301 comprising the power source line (Vcc) 328 and the GND line 329 connected to the diffusion layers 321 and 322 of the transistor layer 300 via the first plug 325, the second word line (2 WL) 330 and the first relay wiring 326. FIG. 18A shows a second wiring level 302 comprising the bit lines (BLN, BLT) 333 and the second relay wiring 334 connected to the first relay wiring 326 via the second plug 327. FIG. 18B shows a third wiring level 303 comprising the ferroelectric capacitor 336 connected to the second relay wiring 334 via the third plug 332 and a fourth wiring level 304 formed thereabove and comprising the plate line (PL) 341 connected to the ferroelectric capacitor 336 via the fourth plug 340. Although not illustrated in the drawing, the ferroelectric capacitor 336 is constituted by a laminated structure of a lower electrode, a ferroelectric insulating film and an upper electrode, the lower electrode is connected to the second relay wiring 334 and the upper electrode is connected to the plate line 341.
When the conventional type Shadow RAM is constituted by utilizing SRAM of the three-layers wiring structure, at the first wiring level 301, whereas the GND line is not present in SRAM, in the case of the conventional type Shadow RAM, the GND line 329 is arranged along with the power source line 328 and the second word line 330. This is because the relay wiring 334 to be connected to the ferroelectric capacitor, is provided at the second wiring level 302. Therefore, there is constituted a layout of a memory cell MC having a size LB in a direction of extending the bit line longer than that of SRAM of the three-layers wiring structure and the cell area of the memory cell MC is increased. This also constitutes a hindrance in achieving high capacity formation of a storage capacitor similar to the conventional type Shadow RAM described above.
It is an object of the invention to provide a semiconductor memory apparatus for preventing an increase in a cell area of a memory cell of a Shadow RAM and achieving high capacity formation of a storage capacitor.
Further, it is an object of the invention to provide a semiconductor memory apparatus capable of designing a Shadow RAM by utilizing design data of a wiring layer of a transistor applied to an SRAM which has been generally used conventionally, as it is.
Further, it is an object of the invention to provide a semiconductor memory apparatus achieving a reduction in a number of steps of design of a Shadow RAM and shortening of a design period of time and having a large storage capacity.
A semiconductor memory apparatus according to the invention includes an SRAM memory cell and a Shadow RAM memory cell. The Shadow RAM memory cell is provided with a ferroelectric capacitor at the SRAM memory cell and is constituted such that an area of the Shadow RAM memory cell is equal to an area of the memory cell of SRAM.
Further, a semiconductor memory apparatus according to the invention at least includes a Shadow RAM having a ferroelectric capacitor at an SRAM memory cell, the Shadow RAM includes a relay wiring layer and two storage nodes of a portion of the SRAM memory cell is connected to the low electric capacitor respectively via a relay wiring of the relay wiring layer and an opening portion. The respective storage nodes and the relay wiring of the relay wiring layer are connected via a first and a second opening portion and the relay wiring and a lower electrode of the ferroelectric capacitor are connected via a third and a fourth opening portion. The relay wiring is provided to make a distance between the third and the fourth opening portions narrower than the distance between the first and the second opening portions.
That is, the relay wiring layer is provided, the relay wiring layer is formed with the relay wiring for connecting an upper layer wiring layer and a lower layer wiring layer in an arbitrary pattern shape and a position of an opening portion for connecting the upper layer wiring layer connected to the relay wiring and a position of an opening portion for connecting the lower layer wiring are set to different arbitrary positions. Thereby, the respective nodes and the lower electrode of the ferroelectric capacitor can be connected without changing almost all data of a wiring layer applied to SRAM which has been generally used conventionally.
Further, the invention is characterized in that a peripheral circuit for driving SRAM and Shadow RAM is commonly used. In this case, there is constructed a constitution in which SRAM and Shadow RAM are present to mix in a memory cell region. Further, a memory cell region constituted by Shadow RAM and a memory cell region constituted by SRAM in either one of a bit line direction or a word line direction, are made the same size.
According to the invention, a number of wiring levels is increased more than that of wiring layers of conventional type Shadow RAM, at the increased wiring layer, a relay wiring for connecting a wiring layer at an upper layer and a wiring layer at a lower layer is formed in an arbitrary shape and a connection structure for connecting the wiring layer at the lower layer and the connection structure for connecting to the wiring layer at the upper layer can be set to different arbitrary positions. Therefore, Shadow RAM can be realized even when layouts of the wiring layer at the upper layer and the wiring layer at the lower layer of the conventional type Shadow RAM are maintained to layouts the same as layouts of corresponding wiring layers of a memory cell of SRAM and the Shadow RAM of the invention can be realized while maintaining a size thereof the same as that of the memory cell of SRAM. Further, by commonly using a peripheral circuit, a semiconductor memory apparatus can easily be designed by substituting a memory cell region of conventional SRAM to Shadow RAM as it is.